John W. Lockwood

John has moved. Click below to visit his
new web homepage at Stanford University
as of January 2007

Current

Lead Consultant and CEO Algo-Logic Systems - Palo Alto, CA Design network algorithms in Logic Provide corporate training on hardware Consult on high-speed network design

Recent

	Consulting Associate Professor Stanford University - Stanford, CA Department of Electrical Engineering High-Performance Networking Group Manage NetFPGA Project
	Associate Professor (with tenure) Washington University , St. Louis, MO Department of Computer Science and Engineering Applied Research Lab (ARL) Director, Reconfigurable Network Group (RNG)

About

• Short Bio
  • Technical background
  • List of papers by topic

• CV
  • Highlights

  • Work Experience
    • Academic and Industry Positions
  • Research
    • Focus
    • Funding
  • Publications and Presentations
    • Journal Publications
    • Full-Length Conference Papers
    • Short Papers
    • Book Chapters
    • Workshops and Tutorials
    • Tech. Reports
    • Thesis
    • Invited Talks
    • Demonstrations
    • In the Press
    • Patents
  • Education and Skills
    • Skills
    • Education
  • Professional Service
    • Leadership
    • Service
    • Membership

• Current Work
  • NetFPGA Project
    Open platform for network switching and routing
  • Reconfigurable Network Group
    (Leader and Principle Investigator)
  • Technologies for Dynamically Extensible Networks
    Extensible services for 10 Gbps+ networks
• Past Work
  • Field-programmable Port Extender (FPX)
    Extensible Network platform in reconfigurable hardware
    enabling flexible packet processing and network security.
  • iPOINT testbed
    Network switching and queueing system implemented
    with Field Programmable Gate Arrays (FPGAs).
  • iWANDER
    Providing Quality of Service (QoS) for a wireless local area networks.

Teaching

• Graduate Research Supervised
  • Doctoral and MS committees: Leadership and Service

• Graduate Courses Created
  • Reconfigurable System-on-Chip Design
    • E81 CSE 566: Fall 2006: Handel-C, Fall 2004: TCP/IP flows, Fall 2002: QoS & SPAM
  • Acceleration of Algorithms in Reconfigurable Hardware
    • E81 CSE 565: Fall 2005: Network Gaming, Fall 2003: Statistics and Bloom Filters, Fall 2001: Protocol Wrappers and HW/SW co-design
  
  
• Graduate Seminars
  • Research Seminar on Networking
    • CSE 770: Spring 2006, Fall 2005, Spring 2005, Fall 2004
  • Research Seminar on Reconfigurable Hardware
    • CSE 681: Spring 2004, Fall 2003, Spring 2003, Fall 2002 , Spring 2002

• Undergraduate Courses Instructed
  • Digital Computers: Switching Theory and Logic Synthesis
    • E65: CSE 460: Spring 2006, Spring 2001
  • Digital Systems Laboratory
    • E61: CSE 465 - Spring 2005
  • Processing Systems and Structures
    • E61: CS/CoE 306 - Spring 2004, Spring 2003, Spring 2002
  • System and Machine-level programming
    • ECE291 (University of Illinois) - Fall 1996 - Spring 1999
  
  

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