CS502 2003 Course Project

Implementing a 1024-bit RSA on FPGA

Jing Lu, Qian Wan

RSA Algorithm Overview:

System Architecture:

Key Generation:

Encryption:

Decryption:

Hardware Implementation:

Random Number Generator:
We implemented a 521-bit Fibonacci Linear Feedback Shift Register (LFSR) to generate 512-bit pseudo random numbers, which are used in primality test.

Simulation Waveforms:
Here are the rand_num_gen_wave_0

512-bit and 1024-bit Addition:
We used Xilinx Core Generator System to first generator a combinatorial 32-bit adder. Then we built our 512-bit and 1024-bit adders by concatenating 16 and 32 32-bit adders, respectively.
Simulation Waveforms:
Here are the add_512_wave_0

Here are the add_512_wave_1

Here are the add_512_wave_2

Here are the add_1024_wave_0

512-bit and 1024-bit Modular Multiplication:
We used binary method to implement modular multiplication. You can find more detail in the report.
Simulation Waveforms:
Here are the mod_mul_512_wave_0

Here are the mod_mul_512_wave_1

Here are the mod_mul_512_wave_2

Here are the mod_mul_1024_wave_0

Here are the mod_mul_1024_wave_1

Here are the mod_mul_1024_wave_2

512-bit and 1024-bit Modular Exponention:
We used binary method to implement modular exponentation. You can find more detail in the report.
Simulation Waveforms:
Here are the mod_exp_512_wave_0

Here are the mod_exp_512_wave_1

Here are the mod_exp_512_wave_2

Here are the mod_exp_1024_wave_0

Here are the mod_exp_1024_wave_1

Here are the mod_exp_1024_wave_2

Primality tester:
We implemented Miller and Rabin's primality test algorithm. You can find more detail in the report.

Simulation Waveforms:
Here are the prime_test_wave_0

Here are the prime_test_wave_1

Here are the prime_test_wave_2

Here are the prime_test_wave_3

Here are the prime_test_wave_4

Here are the prime_test_wave_5

Here are the prime_test_wave_6

Here are the prime_test_wave_7

Here are the prime_test_wave_8

Here are the prime_test_wave_9

Here are the prime_test_wave_10

Greatest Common Divider:
We implemented extended Euler's algorithm. You can find more detail in the report.

Simulation Waveforms:
Here are the gcd_wave_0

Here are the gcd_wave_1

Here are the gcd_wave_2

VHDL Source Code, Testbench, and Makefile: rsa_circuit.zip

Testing: A brief description of the procedures can be found at Testing.doc

Software confirmation of the correctness of the results.
The RSA Java program can be downloaded here: myRSA.java and an example of 1024-bit result sets can be seen here: myRSA result

Documentation:
Project Proposal: proposal.doc

Project Presentation: rsa.ppt

Project Report: report.doc